3D VLSI - Paper Presentation

3D VLSI ( Very Large Scale Integration )

As all of us are well known with the Paper Presentation, paper presentation is important part of engineering. Here is the paper presented by me and my friend on topic 3D VLSI. VLSI means very large scale integration. It is overall depend on the Moore law. Moore’s law was created by Gordon E. Moore, who is the Chairman Emeritus of Intel Corporation. It says that the “The number of transistors on an integrated circuit will double every 18 months.” 3D VLSI is the next step of the VLSI. In VLSI the IC’s are arranged in horizontal order but in 3 dimensional VLSI the IC’s were fabricated vertical order, due to arranging in vertical order the space of the device will be minimum. But there is also limitation for 3D VLSI; we need to increase the level of the device to a particular length. The following is the information about the 3D VLSI

For any query comment below.

Origins of VLSI

—  Much development motivated by WWII need for improved electronics, especially for radar

—  1940 - Russell Ohl (Bell Laboratories) - first pn junction

—  1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor

◦      1956 Nobel Physics Prize

—  Late 1950s - purification of Si advances to acceptable levels for use in electronics

—  1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC 1604

—  1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mm²

—  1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuit

—  1968 - Noyce, Gordon E. Moore found Intel

—  1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm²

—  Since then - continued improvement in technology has allowed for increased performance as predicted by Moore’s Law

Moore’s Law

• Gordon E. Moore - Chairman Emeritus of Intel Corporation

• 1965 - observed trends in industry - # of transistors on ICs vs. release dates:

–  Noticed number of transistors doubling with release of each new IC generation

–   release dates (separate generations) were all 18-24 months apart

•  Moore’s Law:

–  The number of transistors on an integrated circuit will double every 18 months

• The level of integration of silicon technology as measured in terms of number of devices per IC

•  This comes about in two ways – size reduction of the individual devices and increase in the chip or dice size

•  As an indication of size reduction, it is interesting to note that feature size was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, whereas now all features are measured in mm’s (1 mm = 10^-6 m or 10^-4 cm)

•  Semiconductor industry has followed this prediction with surprising accuracy

Limits of Moore’s Law?

 
  — Growth expected until 30 nm gate length (currently: 180 nm)

◦      size halved every 18 mos. - reached in

   2001 + 1.5 log₂((180/30)²) = 2009

◦      what then?

  — Paradigm shift needed in fabrication process

Advantages of 3D VLSI

  — Speed - the time required for a signal to travel between the functional                circuit blocks in a system (delay) reduced.

◦      Delay depends on resistance/capacitance of interconnections

◦      resistance proportional to interconnection length

  — Noise - unwanted disturbances on a useful signal

◦      reflection noise (varying impedance along interconnect)

◦      crosstalk noise (interference between interconnects)

◦      electromagnetic interference (EMI) (caused by current in pins)

   — 3D chips

◦      fewer, shorter interconnects

               ◦      fewer pins 

To Download full Printable Version Click Here : https://www.dropbox.com/s/c68i6snsx82dea3/3D%20VLSI.pdf



Vic